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lt3756/lt3756-1/lt3756-2 375612fb typical a pplica t ion fea t ures a pplica t ions descrip t ion 100v in , 100v out led controller the lt ? 3756, lt3756-1 and lt3756-2 are dc/dc control- lers designed to operate as a constant-current source for driving high current leds. they drive a low side external n-channel power mosfet from an internal regulated 7.15v supply. the fxed frequency, current-mode architecture results in stable operation over a wide range of supply and output voltages. a ground referenced voltage fb pin serves as the input for several led protection features, and also makes it possible for the converter to operate as a constant-voltage source. a frequency adjust pin allows the user to program the frequency from 100khz to 1mhz to optimize effciency, performance or external component size. the lt3756/lt3756-1/lt3756-2 sense output current at the high side of the led string. high side current sensing is the most fexible scheme for driving leds, allowing boost, buck mode or buck-boost mode confguration. the pwm input provides led dimming ratios of up to 3000:1, and the ctrl input provides additional analog dimming capability. 94% effcient 30w white led headlamp driver n 3000:1 true color pwm? dimming n wide input voltage range: 6v to 100v n output voltage up to 100v n constant-current and constant-voltage regulation n 100mv high side current sense n drives leds in boost, buck mode, buck-boost mode, sepic or flyback topology n adjustable frequency: 100khz to 1mhz n open led protection n programmable undervoltage lockout with hysteresis n improved open led status pin (lt3756-2) n frequency synchronization (lt3756-1) n pwm disconnect switch driver n ctrl pin provides analog dimming n low shutdown current: <1a n programmable soft-start n thermally enhanced 16-lead qfn (3mm 3mm) and msop packages n high power led applications n current limited constant voltage applications n battery charging v in lt3756-2 22h gnd v c intv cc shdn /uvlo fb v ref isp 332k 100k intv cc 1m 4.7f 0.001f 0.01f v in 8v to 60v (100v transient) 185k 10k 28.7k 375khz 1% 4.7f intv cc 40.2k ctrl 0.018 0.27 1m 14k 370ma 4.7f 30w led string 375612 ta01a openled pwm ss rt isn gate sense pwmout effciency vs v in v in (v) 0 20 80 efficiency (%) 84 88 92 96 100 40 60 80 375612 ta01b l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. true color pwm is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7199560 and 7321203.
lt3756/lt3756-1/lt3756-2 375612fb a bsolu t e maxi m u m r a t ings v in ..........................................................................100v shdn/uvlo ............................................................100v isp, isn ...................................................................100v intv cc ...................................................... v in + 0.3v, 8v gate, pwmout (note 4) ..........................intv cc + 0.3v ctrl, pwm, openled .............................................12v vc, v ref , ss, fb .........................................................3v sync ..........................................................................8v (note 1) o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt3756emse#pbf lt3756emse#trpbf 3756 16-lead plastic msop C40c to 125c lt3756imse#pbf lt3756imse#trpbf 3756 16-lead plastic msop C40c to 125c lt3756emse-1#pbf lt3756emse-1#trpbf 37561 16-lead plastic msop C40c to 125c lt3756imse-1#pbf lt3756imse-1#trpbf 37561 16-lead plastic msop C40c to 125c lt3756emse-2#pbf lt3756emse-2#trpbf 37562 16-lead plastic msop C40c to 125c lt3756imse-2#pbf lt3756imse-2#trpbf 37562 16-lead plastic msop C40c to 125c lt3756hmse-2#pbf lt3756hmse-2#trpbf 37562 16-lead plastic msop C40c to 150c lt3756eud#pbf lt3756eud#trpbf ldmq 16-lead (3mm 3mm) plastic qfn C40c to 125c lt3756iud#pbf lt3756iud#trpbf ldmq 16-lead (3mm 3mm) plastic qfn C40c to 125c lt3756eud-1#pbf lt3756eud-1#trpbf ldmr 16-lead (3mm 3mm) plastic qfn C40c to 125c lt3756iud-1#pbf lt3756iud-1#trpbf ldmr 16-lead (3mm 3mm) plastic qfn C40c to 125c lt3756eud-2#pbf lt3756eud-2#trpbf lfkb 16-lead (3mm 3mm) plastic qfn C40c to 125c lt3756iud-2#pbf lt3756iud-2#trpbf lfkb 16-lead (3mm 3mm) plastic qfn C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ 1 2 3 4 5 6 7 8 pwmout fb isn isp vc ctrl v ref pwm 16 15 14 13 12 11 10 9 gate sense v in intv cc shdn /uvlo rt ss sync or openled top view 17 gnd mse package 16-lead plastic msop t jmax = 125c (e-,i-grades), t jmax = 150c (h-grade), ja = 43c/w, jc = 4c/w exposed pad (pin 17) is gnd, must be soldered to pcb 16 15 14 13 5 6 7 8 top view 17 gnd ud package 16-lead (3mm s 3mm) plastic qfn 9 10 11 12 4 3 2 1v ref pwm sync or openled ss fb pwmout gate sense ctrl vc isp isn rt shdn/uvlo intv cc v in t jmax = 125c, ja = 68c/w, jc = 4.2c/w exposed pad (pin 17) is gnd, must be soldered to pcb p in c on f igura t ion rt ............................................................................1.5v sense ......................................................................0.5v operating junction temperature range (notes 2, 3) l t3756e, l t3756i .............................. C40c to 125c l t3756h ............................................ C40c to 150c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) mse .................................................................. 300c
lt3756/lt3756-1/lt3756-2 375612fb e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 24v, shdn /uvlo = 24v, ctrl = 2v, pwm = 5v, unless otherwise noted. parameter conditions min typ max units v in minimum operating voltage v in tied to intv cc l 6 v v in shutdown i q shdn /uvlo = 0v, pwm = 0v shdn /uvlo = 1.15v, pwm = 0v 0.1 1 5 a a v in operating i q (not switching) pwm = 0v 1.4 1.7 ma v ref voltage 100a i vref 0a l 1.965 2.00 2.045 v v ref line regulation 6v v in 100v 0.006 %/v sense current limit threshold l 98 108 118 mv sense input bias current current out of pin 40 a ss pull-up current current out of pin 8 10 13 a error amplifer isp/isn full-scale current sense threshold fb = 0v, isp = 48v l 96 100 103 mv isp/isn current sense threshold at ctrl = 0v ctrl = 0v, fb = 0v, isp = 48v C12 C9.5 C7 mv ctrl pin range for current sense threshold adjustment l 0 1.1 v ctrl input bias current current out of pin 50 100 na led current sense amplifer input common mode range (v isn ) l 2.9 100 v isp/isn short-circuit threshold isn = 0v 115 150 200 mv isp/isn short-circuit fault sensing common mode range (v isn ) l 0 3 v isp/isn input bias current (combined) pwm = 5v (active), isp = isn = 48v pwm = 0v (standby), isp = isn = 48v 55 0 0.1 a a led current sense amplifer g m v (isp C isn) = 100mv 120 s vc output impedance 1v < vc < 2v 15000 k vc standby input bias current pwm = 0v C20 20 na fb regulation voltage (v fb ) isp = isn l 1.220 1.232 1.250 1.250 1.270 1.265 v v fb amplifer g m fb = v fb , isp = isn 480 s fb pin input bias current current out of pin 40 100 na fb open led threshold openled falling (lt3756 and lt3756-2) v fb C 65mv v fb C 50mv v fb C 40mv v fb overvoltage threshold pwmout falling v fb + 50mv v fb + 60mv v fb + 75mv v vc current mode gain C (?v vc /?v sense ) 4 v/v oscillator switching frequency r t = 100k r t = 10k l 90 925 100 1000 125 1050 khz khz minimum off-time 170 ns linear regulator intv cc regulation voltage 7 7.15 7.3 v dropout (v in C intv cc ) i intvcc = C10ma, v in = 7v 1 v intv cc undervoltage lockout 3.9 4.1 4.3 v intv cc current limit 14 17 23 ma intv cc current in shutdown shdn /uvlo = 0v, intv cc = 7v 8 12 a
lt3756/lt3756-1/lt3756-2 375612fb e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 24v, shdn /uvlo = 24v, ctrl = 2v, pwm = 5v, unless otherwise noted. parameter conditions min typ max units logic inputs/outputs pwm input high voltage l 1.5 v pwm input low voltage l 0.4 v pwm pin resistance to gnd 45 60 k pwmout output low (v ol ) 0 50 mv pwmout output high (v oh ) intv cc C 0.05 v shdn /uvlo threshold voltage falling e-, i-grades h grade l l 1.185 1.175 1.220 1.245 1.245 v v shdn/uvlo rising hysteresis 20 mv shdn /uvlo input low voltage i vin drops below 1a 0.4 v shdn/uvlo pin bias current low shdn/uvlo = 1.15v 1.7 2.05 2.5 a shdn/uvlo pin bias current high shdn/uvlo = 1.30v 10 100 na openled output low (v ol ) i openled = 0.5ma (lt3756 and lt3756-2) 200 mv sync pin resistance to gnd lt3756-1 only 30 k sync input high lt3756-1 only 1.5 v sync input low lt3756-1 only 0.4 v gate driver t r gate driver output rise time c l = 3300pf 35 ns t f gate driver output fall time c l = 3300pf 35 ns gate output low (v ol ) 0.05 v gate output high (v oh ) intv cc C 0.05 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3756e, lt3756e-1 and lt3756e-2 are guaranteed to meet performance specifcations from 0c to 125c junction temperature. specifcations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3756i, lt3756i-1 and lt3756i-2 are guaranteed to meet performance specifcations over the C40c to 125c operating junction temperature range. the lt3756h-2 is guaranteed to meet performance specifcations over the full C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note 3: the lt3756 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. continuous operating above the specifed maximum operating junction temperature may impair device reliability. note 4: gate and pwmout pins are driven either to gnd or intv cc by internal switches. do not connect these pins externally to a power supply.
lt3756/lt3756-1/lt3756-2 375612fb typical p er f or m ance c harac t eris t ics fb regulation voltage vs temperature v ref voltage vs temperature v ref voltage vs v in switching frequency vs r t switching frequency vs temperature shdn/uvlo hysteresis current vs temperature v (isp C isn) threshold vs v ctrl v (isp C isn) threshold vs v isp v (isp C isn) threshold vs temperature t a = 25c, unless otherwise noted. r t (k) switching frequency (khz) 375612 g07 10000 1000 100 10 10 100 v ctrl (v) 0 ?20 v (isp ? isn) threshold (mv) 20 60 100 0.5 1 1.5 120 0 40 80 2 375612 g01 isp voltage (v) 0 97 v (isp ? isn) threshold (mv) 99 101 20 40 8060 103 98 100 102 100 375612 g02 v ctrl = 2v 97 99 101 103 98 100 102 375612 g03 v (isp ? isn) threshold (mv) temperature (c) ?50 0 50 75 ?25 25 100 150125 v ctrl = 2v 375612 g04 v fb (v) temperature (c) ?50 0 50 75 ?25 25 100 150125 1.20 1.22 1.24 1.26 1.28 1.21 1.23 1.25 1.27 375612 g05 v ref (v) temperature (c) ?50 0 50 75 ?25 25 100 150125 1.96 1.98 2.00 2.02 2.04 1.97 1.99 2.01 2.03 v in (v) 0 1.96 v ref (v) 1.98 2.00 2.02 20 40 100 60 80 2.04 1.97 1.99 2.01 2.03 375612 g06 375612 g08 switching frequency (khz) temperature (c) ?50 0 50 75 ?25 25 100 150125 300 350 400 450 500 r t = 26.7k 375612 g09 temperature (c) ?50 0 50 75 ?25 25 100 150125 1.6 i shdn/uvlo (a) 2.0 2.4 1.8 2.2
lt3756/lt3756-1/lt3756-2 375612fb typical p er f or m ance c harac t eris t ics intv cc voltage vs v in intv cc current limit vs temperature intv cc voltage vs temperature quiescent current vs v in sense current limit threshold vs temperature shdn/uvlo threshold vs temperature t a = 25c, unless otherwise noted. 375612 g11 sense threshold (mv) temperature (c) 90 100 110 95 105 ?50 0 50 75 ?25 25 100 150125 375612 g12 shdn/uvlo voltage (v) temperature (c) 1.18 1.22 1.28 1.20 1.24 1.26 shdn/uvlo rising shdn/uvlo falling ?50 0 50 75 ?25 25 100 150125 gate rise/fall time vs capacitance sense current limit threshold vs duty cycle v (isp-isn) threshold vs fb voltage v in (v) 0 v in current (ma) 1.0 2.0 0.5 1.5 375612 g10 0 20 40 8060 100 pwm = 0v v in (v) v intvcc (v) 375612 g13 0 4 8 2 6 0 20 40 8060 100 375612 g14 intv cc current limit (ma) temperature (c) 10 14 20 12 16 18 ?50 0 50 75 ?25 25 100 150125 375612 g15 intv cc (v) temperature (c) ?50 0 50 75 ?25 25 100 150125 7.0 7.2 7.4 7.1 7.3 duty cycle (%) 90 sense threshold (mv) 100 110 95 105 375612 g16 0 25 50 75 100 fb voltage (v) 375612 g17 1.2 1.22 1.24 1.26 1.28 0 50 125 25 75 100 v (isp ?isn) threshold (mv) v ctrl = 2v capacitance (nf) 375612 g18 0 2 4 6 108 0 40 100 20 60 80 time (ns) gate rise time gate fall time 10% to 90%
lt3756/lt3756-1/lt3756-2 375612fb p in func t ions pwmout (pin 1/pin 11): buffered version of pwm signal for driving led load disconnect nmos or level shift. this pin also serves in a protection function for the fb overvoltage conditionwill toggle if the fb input is greater than the fb regulation voltage (v fb ) plus 60mv (typical). the pwmout pin is driven from intv cc . use of a fet with gate cut-off voltage higher than 1v is recommended. fb (pin 2/pin 12): voltage loop feedback pin. fb is intended for constant-voltage regulation or for led protec- tion/open led detection. the internal transconductance amplifer with output vc will regulate fb to 1.25v (nominal) through the dc/dc converter. if the fb input is regulating the loop, the openled pull-down is asserted. this ac- tion may signal an open led fault. if fb is driven above the fb threshold (by an external power supply spike, for example), the openled pull-down will be de-asserted and the pwmout pin will be driven low to protect the leds from an overcurrent event. do not leave the fb pin open. if not used, connect to gnd. isn (pin 3/pin 13): connection point for the negative terminal of the current feedback resistor. if isn is greater than 2.9v, the led current can be programmed by i led = 100mv/r led when v ctrl > 1.2v or i led = (v ctrl C100mv)/ (10 ? r led ) when v ctrl 1v. input bias current is typi- cally 25a. below 3v, isn is an input to the short-circuit protection feature that forces gate to 0v if isp exceeds isn by more than 150mv (typ). isp (pin 4/pin 14): connection point for the positive terminal of the current feedback resistor. input bias current is dependent upon ctrl pin voltage as shown in the tpc. isp is an input to the short-circuit protection feature when isn is less than 3v. vc (pin 5/pin 15): transconductance error amplifer output pin used to stabilize the voltage loop with an rc network. this pin is high impedance when pwm is low, a feature that stores the demand current state variable for the next pwm high transition. connect a capacitor between this pin and gnd; a resistor in series with the capacitor is recommended for fast transient response. (msop/qfn) typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted. isp/isn input bias current vs ctrl voltage intv cc dropout voltage vs current, temperature ctrl (v) 375612 g19 0 0.5 1 1.5 2 0 20 40 10 30 input bias current (a) isp isn ldo current (ma) 375612 g20 0 3 6 9 12 15 ?2.5 ?1.0 0 ?1.5 ?2.0 ?0.5 ldo dropout (v) ?45c 125c v in = 7v 25c 150c
lt3756/lt3756-1/lt3756-2 375612fb ctrl (pin 6/pin 16): current sense threshold adjustment pin. regulating threshold v (isp C isn) is 1/10th v ctrl plus an offset for 0v < v ctrl < 1v. for v ctrl > 1.2v the current sense threshold is constant at the full-scale value of 100mv. for 1v < v ctrl < 1.2v, the dependence of current sense threshold upon v ctrl transitions from a linear function to a constant value, reaching 98% of full-scale value by v ctrl = 1.1v. do not leave this pin open. v ref (pin 7/pin 1): voltage reference output pin, typically 2v. this pin drives a resistor divider for the ctrl pin, either for analog dimming or for temperature limit/compensation of led load. can supply up to 100a. pwm (pin 8/pin 2): a signal low turns off switcher, idles oscillator and disconnects vc pin from all internal loads. pwmout pin follows pwm pin. pwm has an internal pull-down resistor. if not used, connect to intv cc . openled (pin 9/pin 3, lt3756 and lt3756-2): an open- collector pull-down on openled asserts if the fb input is greater than the fb regulation threshold minus 50mv (typical). to function, the pin requires an external pull-up current less than 1ma. when the pwm input is low and the dc/dc converter is idle, the openled condition is latched to the last valid state when the pwm input was high. when pwm input goes high again, the openled pin will be updated. this pin may be used to report an open led fault. sync (pin 9/pin 3, lt3756-1 only): the sync pin is used to synchronize the internal oscillator to an external logic level signal. the r t resistor should be chosen to program an internal switching frequency 20% slower than the sync pulse frequency. gate turn-on occurs a fxed delay after the rising edge of sync. for best pwm performance, the pwm rising edge should occur at least 200ns before the sync rising edge. use a 50% duty cycle waveform to drive this pin. this pin replaces openled on lt3756-1 option parts. if not used, tie this pin to gnd. ss (pin 10/pin 4): soft-start pin. this pin modulates oscillator frequency and compensation pin voltage (vc) clamp. the soft-start interval is set with an external capaci- tor. the pin has a 10a (typical) pull-up current source to an internal 2.5v rail. the soft-start pin is reset to gnd by an undervoltage condition (detected by shdn/uvlo pin) or thermal limit. rt (pin 11/pin 5): switching frequency adjustment pin. set the frequency using a resistor to gnd (for resistor values, see the typical performance curve or table 1). do not leave the rt pin open. shdn /uvlo (pin 12/pin 6): shutdown and undervoltage detect pin. an accurate 1.22v falling threshold with ex- ternally programmable hysteresis detects when power is ok to enable switching. rising hysteresis is generated by the external resistor divider and an accurate internal 2.1a pull-down current. above the threshold (but below 6v), shdn /uvlo input bias current is sub-a. below the falling threshold, a 2.1a pull-down current is enabled so the user can defne the hysteresis with the external resis- tor selection. an undervoltage condition resets soft-start. tie to 0.4v, or less, to disable the device and reduce v in quiescent current below 1a. intv cc (pin 13/pin 7): regulated supply for internal loads, gate driver and pwmout driver. supplied from v in and regulates to 7.15v (typical). intv cc must be bypassed with a 4.7f capacitor placed close to the pin. connect intv cc directly to v in if v in is always less than or equal to 8v. v in (pin 14/pin 8): input supply pin. must be locally bypassed with a 0.22f (or larger) capacitor placed close to the ic. sense (pin 15/pin 9): the current sense input for the control loop. kelvin connect this pin to the positive ter- minal of the switch current sense resistor, r sense , in the source of the nfet. the negative terminal of the current sense resistor should be connected to the gnd plane close to the ic. gate (pin 16/pin 10): n-channel fet gate driver output. switches between intv cc and gnd. driven to gnd during shutdown, fault or idle states. gnd (pin 17/pin 17): ground. this pin also serves as current sense input for control loop, sensing negative terminal of current sense resistor. solder the exposed pad directly to ground plane. p in func t ions
lt3756/lt3756-1/lt3756-2 375612fb b lock diagra m + ? + ? + ? + ? + ? + + ? a1 a3 a6 + + ? freq prog 1.25v ssclamp 1.1v ctrl v ref shdn/uvlo isp isn q2 150mv 50k 170k 140a 2.1a ctrl buffer g m eamp pwm comparator driver i sense a4 g m a10 a5 ovfb comparator 1.25v fb short-circuit detect (lt3756 and lt3756-2) scilmb scilmb 5k pwmout pwm 1.25v v in intv cc vc + ? + ? a2 r q s ramp generator 100khz to 1mhz oscillator + ? + ? a8 7.15v ldo gate sense 375612 bd openled gnd 1.2v fb + ? 1.22v + ? 2v 1.3v rt sync (lt3756-1 only) ss shdn a7 10a 10a at fb = 1.25v vc t lim 165c fault logic 10a 10a at a1 + = a1 ?
lt3756/lt3756-1/lt3756-2 0 375612fb o pera t ion the lt3756 is a constant-frequency, current mode control- ler with a low side nmos gate driver. the gate pin and pwmout pin drivers, and other chip loads, are powered from intv cc , which is an internally regulated supply. in the discussion that follows, it will be helpful to refer to the block diagram of the ic. in normal operation, with the pwm pin low, the gate and pwmout pins are driven to gnd, the vc pin is high impedance to store the previous switching state on the external compensation capacitor, and the isp and isn pin bias currents are reduced to leakage levels. when the pwm pin transitions high, the pwmout pin transitions high after a short delay. at the same time, the internal oscillator wakes up and gener- ates a pulse to set the pwm latch, turning on the external power mosfet switch (gate goes high). a voltage input proportional to the switch current, sensed by an external current sense resistor between the sense and gnd input pins, is added to a stabilizing slope compensation ramp and the resulting switch current sense signal is fed into the positive terminal of the pwm comparator. the current in the external inductor increases steadily during the time the switch is on. when the switch current sense voltage exceeds the output of the error amplifer, labeled vc, the latch is reset and the switch is turned off. during the switch off phase, the inductor current decreases. at the completion of each oscillator cycle, internal signals such as slope compensation return to their starting points and a new cycle begins with the set pulse from the oscillator. through this repetitive action, the pwm control algorithm establishes a switch duty cycle to regulate a current or voltage in the load. the vc signal is integrated over many switching cycles and is an amplifed version of the differ- ence between the led current sense voltage, measured between isp and isn, and the target difference voltage set by the ctrl pin. in this manner, the error amplifer sets the correct peak switch current level to keep the led current in regulation. if the error amplifer output increases, more current is demanded in the switch; if it decreases, less current is demanded. the switch current is monitored during the on-phase and the voltage across the sense pin is not allowed to exceed the current limit threshold of 108mv (typical). if the sense pin exceeds the current limit threshold, the sr latch is reset regard- less of the output state of the pwm comparator. likewise, at an isp/isn common mode voltage less than 3v, the difference between isp and isn is monitored to determine if the output is in a short-circuit condition. if the difference between isp and isn is greater than 150mv (typical), the sr latch will be reset regardless of the pwm comparator. these functions are intended to protect the power switch, as well as various external components in the power path of the dc/dc converter. in voltage feedback mode, the operation is similar to that described above, except the voltage at the vc pin is set by the amplifed difference of the internal reference of 1.25v (nominal) and the fb pin. if fb is lower than the reference voltage, the switch current will increase; if fb is higher than the reference voltage, the switch demand current will decrease. the led current sense feedback interacts with the fb voltage feedback so that fb will not exceed the internal reference and the voltage between isp and isn will not exceed the threshold set by the ctrl pin. for accurate current or voltage regulation, it is necessary to be sure that under normal operating conditions, the appropriate loop is dominant. to deactivate the voltage loop entirely, fb can be connected to gnd. to deactivate the led current loop entirely, the isp and isn should be tied together and the ctrl input tied to v ref . two led specifc functions featured on the lt3756 are controlled by the voltage feedback pin. first, when the fb pin exceeds a voltage 50mv lower (C4%) than the fb regulation voltage, the pull-down driver on the openled pin is activated (lt3756 and lt3756-2 only). this function provides a status indicator that the load may be discon- nected and the constant-voltage feedback loop is taking control of the switching regulator. when the fb pin exceeds the fb regulation voltage by 60mv (5% typical), the pwm- out pin is driven low, ignoring the state of the pwm input. in the case where the pwmout pin drives a disconnect nfet, this action isolates the led load from gnd, prevent- ing excessive current from damaging the leds. if the fb input exceeds both the open led and the overvoltage thresholds, then an externally driven overvoltage event has caused the fb pin to be too high and the openled pull-down will be de-asserted. the lt3756-2 will re-assert the openled signal when fb falls below the overvoltage threshold and remains above the open led threshold. the lt3756 is prevented from re-asserting openled until fb drops below both thresholds.
lt3756/lt3756-1/lt3756-2 375612fb a pplica t ions i n f or m a t ion intv cc regulator bypassing and operation the intv cc pin requires a capacitor for stable operation and to store the charge for the large gate switching cur- rents. choose a 10v rated low esr, x7r or x5r ceramic capacitor for best performance. a 4.7f capacitor will be adequate for many applications. place the capacitor close to the ic to minimize the trace length to the intv cc pin and also to the ic ground. an internal current limit on the intv cc output protects the lt3756 from excessive on-chip power dissipation. the minimum value of this current should be considered when choosing the switching nmos and the operating frequency. i intvcc can be calculated from the following equation: i intvcc = q g ? f osc careful choice of a lower q g fet will allow higher switch- ing frequencies, leading to smaller magnetics. the intv cc pin has its own undervoltage disable (uvlo) set to 4.1v (typical) to protect the external fets from excessive power dissipation caused by not being fully enhanced. if the intv cc pin drops below the uvlo threshold, the gate and pwmout pins will be forced to 0v and the soft-start pin will be reset. if the input voltage, v in , will not exceed 8v, then the intv cc pin could be connected to the input supply. be aware that a small current (less than 12a) will load the intv cc in shutdown. if v in is normally above, but occasionally drops below the intv cc regulation voltage, then the minimum operating v in will be close to 7v . this value is determined by the dropout voltage of the linear regulator and the 4.5v (4.1v typical) intv cc undervoltage lockout threshold mentioned above. programming the turn-on and turn-off thresholds with the shdn/uvlo pin the falling uvlo value can be accurately set by the resistor divider. a small 2.1a pull-down current is active when shdn /uvlo is below the threshold. the purpose of this current is to allow the user to program the rising hysteresis. shdn/uvlo lt3756 v in r2 375612 f01 r1 figure 1. resistor connection to set v in undervoltage shutdown threshold the following equations should be used to determine the values of the resistors: v in,falling = 1.22 ? r1 + r2 r2 v in,rising = 2.1a ? r1 + v in,falling led current programming the led current is programmed by placing an appropriate value current sense resistor, r led , in series with the led string. the voltage drop across r led is (kelvin) sensed by the isp and isn pins. typically, sensing of the current should be done at the top of the led string. if this option is not available, then the current may be sensed at the bottom of the string, but take caution that the minimum isn value does not fall below 3v, which is the lower limit of the led current regulation function. the ctrl pin should be tied to a voltage higher than 1.1v to get the full-scale 100mv (typical) threshold across the sense resistor. the ctrl pin can also be used to dim the led current to zero, although relative accuracy decreases with the decreasing voltage sense threshold. when the ctrl pin voltage is less than 1.0v, the led current is: i led = v ctrl ? 100mv r led ? 10 when the ctrl pin voltage is between 1v and 1.2v the led current varies with ctrl, but departs from the equation above by an increasing amount as ctrl voltage increases. ultimately, above ctrl = 1.2v the led current no longer varies with ctrl. at ctrl = 1.1v, the actual value of i led is ~98% of the equations estimate.
lt3756/lt3756-1/lt3756-2 375612fb a pplica t ions i n f or m a t ion when v ctrl is higher than 1.2v, the led current is regu- lated to: i led = 100mv r led the led current programming feature can increase total dimming range by a factor of 10. the ctrl pin should not be left open (tie to v ref if not used). the ctrl pin can also be used in conjunction with a thermistor to provide overtemperature protection for the led load, or with a resistor divider to v in to reduce output power and switching current when v in is low. the presence of a time varying differential voltage signal (ripple) across isp and isn at the switching frequency is expected. the amplitude of this signal is increased by high led load current, low switching frequency and/or a smaller value output flter capacitor. some level of ripple signal is acceptable: the compensation capacitor on the vc pin flters the signal so the average difference between isp and isn is regulated to the user-programmed value. ripple voltage amplitude (peak-to-peak) in excess of 20mv should not cause mis- operation, but may lead to noticeable offset between the average value and the user-programmed value. programming output voltage (constant-voltage regulation) or open led/overvoltage threshold for a boost or sepic application, the output voltage can be set by selecting the values of r3 and r4 (see figure 2) according to the following equation: v out = 1.25 ? r3 + r4 r4 for a boost type led driver, set the resistor from the output to the fb pin such that the expected v fb during normal fb lt3756 v in r4 375612 f02 r3 figure 2. feedback resistor connection for boost or sepic led drivers fb lt3756 100k v out r4 375612 f03 r3 led array r sen(ext) c out + ? figure 3. feedback resistor connection for buck mode or buck-boost mode led driver operation will not exceed 1.1v. for an led driver of buck or a buck-boost confguration, the output voltage is typically level-shifted to a signal with respect to gnd as illustrated in figure 3. the output can be expressed as: v out = v be + 1.25 ? r3 r4 isp/isn short-circuit protection feature (for sepic) the isp and isn pins have a protection feature indepen- dent of the led current sense feature that operates at isn below 3v. the purpose of this feature is to provide continuous current sensing when isn is below the led current sense common mode range (during start-up or an output short-circuit fault) to prevent the development of excessive switching currents that could damage the power components in a sepic converter. the action threshold (150mv, typ) is above the default led current sense threshold, so that no interference will occur over the isn voltage range where these two functions overlap. this feature acts in the same manner as sense current limit it prevents gate from going high (switch turn-on) until the isp/isn difference falls below the threshold. if the load has appreciable series inductance, use of a schottky clamp from gnd to isn is recommended for the sepic to prevent excessive current fowing from the isn pin in a fault. dimming control there are two methods to control the current source for dimming using the lt3756. one method uses the ctrl pin to adjust the current regulated in the leds. a second
lt3756/lt3756-1/lt3756-2 375612fb a pplica t ions i n f or m a t ion method uses the pwm pin to modulate the current source between zero and full current to achieve a precisely pro- grammed average current. to make pwm dimming more accurate, the switch demand current is stored on the vc node during the quiescent phase when pwm is low. this feature minimizes recovery time when the pwm signal goes high. to further improve the recovery time, a disconnect switch may be used in the led current path to prevent the isp node from discharging during the pwm signal low phase. the minimum pwm on or off time will depend on the choice of operating frequency and external component selection. with operation in discontinuous conduction mode (dcm), regulated current pulses as short as 1s are achievable. but, the best overall combination of pwm and analog dimming (with ctrl) is available if the minimum pwm pulse is at least six switching cycles. programming the switching frequency the rt frequency adjust pin allows the user to program the switching frequency from 100khz to 1mhz to optimize effciency/performance or external component size. higher frequency operation yields smaller component size but increases switching losses and gate driving current, and may not allow suffciently high or low duty cycle operation. lower frequency operation gives better performance at the cost of larger external component size. for an appropriate r t resistor value see table 1. an external resistor from the rt pin to gnd is requireddo not leave this pin open. table 1. switching frequency vs r t value f osc (khz) r t (k) 1000 10.0 900 11.8 800 13.0 700 15.4 600 17.8 500 21.0 400 26.7 300 35.7 200 53.6 100 100 duty cycle considerations switching duty cycle is a key variable defning converter operation, therefore, its limits must be considered when programming the switching frequency for a particular application. the fxed minimum on-time and minimum off-time (see figure 4) and the switching frequency defne the minimum and maximum duty cycle of the switch, respectively. the following equations express the mini- mum/maximum duty cycle: min duty cycle = (minimum on-time) ? switching fre- quency max duty cycle = 1 C (minimum off-time) ? switching frequency when calculating the operating limits, the typical values for on/off-time in the data sheet should be increased by at least 60ns to allow margin for pwm control latitude, gate rise/fall times and sw node rise/fall times. 0 100 200 300 50 150 250 375612 f04 time (ns) temperature (c) ?50 0 50 75 ?25 25 100 150125 minimum on-time minimum off-time c gate = 3300pf figure 4. typical minimum on and off pulse width vs temperature thermal considerations the lt3756 series is rated to a maximum input voltage of 100v. careful attention must be paid to the internal power dissipation of the ic at higher input voltages to ensure that a junction temperature of 125c (150c for h-grade) is not exceeded. this junction limit is especially
lt3756/lt3756-1/lt3756-2 375612fb a pplica t ions i n f or m a t ion important when operating at high ambient temperatures. the majority of the power dissipation in the ic comes from the supply current needed to drive the gate capacitance of the external power mosfet. this gate drive current can be calculated as: i gate = f sw ? q g a low q g power mosfet should always be used when op- erating at high input voltages, and the switching frequency should also be chosen carefully to ensure that the ic does not exceed a safe junction temperature. the internal junc- tion temperature of the ic can be estimated by: t j = t a + [v in (i q + f sw ? q g ) ? ja ] where t a is the ambient temperature, i q is the quiescent current of the part (maximum 1.5ma) and ja is the package thermal impedance (68c/w for the 3mm 3mm qfn package). for example, an application with t a(max) = 85c, v in(max) = 60v, f sw = 400khz, and having a fet with q g = 20nc, the maximum ic junction temperature will be approximately: t j = 85c + [60v (1.5ma + 400khz ? 20nc) ? 68c/w] = 124c the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should then be connected to an internal copper ground plane with thermal vias placed directly under the package to spread out the heat dissipated by the ic. if lt3756 junction temperature reaches 165c, the gate and pwmout pins will be driven to gnd and the soft- start (ss) pin will be discharged to gnd. switching will be enabled after device temperature is reduced 10c. this function is intended to protect the device during momentary thermal overload conditions. frequency synchronization (lt3756-1 only) the lt3756-1 switching frequency can be synchronized to an external clock using the sync pin. for proper operation, the r t resistor should be chosen for a switching frequency 20% lower than the external clock frequency. the sync pin is disabled during the soft-start period. observation of the following guidelines about the sync waveform will ensure proper operation of this feature. driving sync with a 50% duty cycle waveform is always a good choice, otherwise, maintain the duty cycle between 20% and 60%. when using both pwm and sync features, the pwm signal rising edge should occur at least 200ns before the sync rising edge (v ih ) for optimal pwm performance. if the sync pin is not used, it should be connected to gnd. open led detection (lt3756 and lt3756-2) the lt3756 and lt3756-2 provide an open-collector status pin, openled , that pulls low when the fb pin is within ~50mv of its 1.25v regulated voltage. if the open led clamp voltage is programmed correctly using the fb pin, then the fb pin should never exceed 1.1v when leds are connected, therefore, the only way for the fb pin to be within 50mv of the regulation voltage is for an open led event to have occurred. the key difference between the lt3756 and lt3756-2 is the behavior of the openled pin when the fb pin crosses and re-crosses the fb overvoltage threshold at 1.31v (typ). the lt3756 - 2 asserts/de-asserts openled freely when crossing the 1.31v threshold. the lt3756, by comparison, de-asserts openled when fb exceeds 1.31v and is prevented from re-asserting openled until the fb pin falls below the 1.2v (typ) open led threshold and clears the fault. the lt3756-2 has the more general purpose behavior and is recommended for applications using openled. input capacitor selection the input capacitor supplies the transient input current for the power inductor of the converter and must be placed and sized according to the transient current requirements. the switching frequency, output current and tolerable input voltage ripple are key inputs to estimating the capacitor value. an x7r type ceramic capacitor is usually the best choice since it has the least variation with temperature and dc bias. typically, boost and sepic converters re- quire a lower value capacitor than a buck mode converter. assuming that a 100mv input voltage ripple is acceptable, the required capacitor value for a boost converter can be estimated as follows: c in (f) = i led (a) ? v out v in ? t sw (s) ? 1f a ? s
lt3756/lt3756-1/lt3756-2 375612fb a pplica t ions i n f or m a t ion therefore, a 4.7f capacitor is an appropriate selection for a 400khz boost regulator with 12v input, 48v output and 1a load. with the same v in voltage ripple of 100mv, the input capaci- tor for a buck converter can be estimated as follows: c in (f) = i led (a) ? t sw (s) ? 4.7f a ? s a 10f input capacitor is an appropriate selection for a 400khz buck mode converter with a 1a load. in the buck mode confguration, the input capacitor has large pulsed currents due to the current returned through the schottky diode when the switch is off. in this buck converter case it is important to place the capacitor as close as possible to the schottky diode and to the gnd return of the switch (i.e., the sense resistor). it is also important to consider the ripple current rating of the capacitor. for best reliability, this capacitor should have low esr and esl and have an adequate ripple current rating. the rms input current for a buck mode led driver is: i in(rms) = i led ? 1? d ( ) ? d where d is the switch duty cycle. table 2. recommended ceramic capacitor manufacturers manufacturer web tdk www.tdk.com kemet www.kemet.com murata www.murata.com taiyo yuden www.t-yuden.com output capacitor selection the selection of the output capacitor depends on the load and converter confguration, i.e., step-up or step-down and the operating frequency. for led applications, the equivalent resistance of the led is typically low and the output flter capacitor should be sized to attenuate the current ripple. use of an x7r type ceramic capacitor is recommended. to achieve the same led ripple current, the required flter capacitor is larger in the boost and buck-boost mode ap- plications than that in the buck mode applications. lower operating frequencies will require proportionately higher capacitor values. soft-start capacitor selection for many applications, it is important to minimize the inrush current at start-up. the built-in soft-start circuit signifcantly reduces the start-up current spike and output voltage overshoot. the soft-start interval is set by the soft- start capacitor selection according to the equation: t ss = c ss ? 2v 10a a typical value for the soft-start capacitor is 0.01f. the soft-start pin reduces the oscillator frequency and the maximum current in the switch. the soft-start capacitor is discharged when shdn /uvlo falls below its threshold, during an overtemperature event or during an intv cc undervoltage event. during start-up with shdn/uvlo, charging of the soft-start capacitor is enabled after the frst pwm high period. power mosfet selection for applications operating at high input or output voltages, the power nmos fet switch is typically chosen for drain voltage v ds rating and low gate charge q g . consideration of switch on-resistance, r ds(on) , is usually secondary be- cause switching losses dominate power loss. the intv cc regulator on the lt3756 has a fxed current limit to protect the ic from excessive power dissipation at high v in , so the fet should be chosen so that the product of q g at 7v and switching frequency does not exceed the intv cc current limit. for driving leds be careful to choose a switch with a v ds rating that exceeds the threshold set by the fb pin in case of an open-load fault. several mosfet vendors are listed in table 3. the mosfets used in the application circuits in this data sheet have been found to work well with the lt3756. consult factory applications for other recommended mosfets. table 3. mosfet manufacturers vendor web vishay siliconix www.vishay.com fairchild www.fairchildsemi.com international rectifer www.irf.com
lt3756/lt3756-1/lt3756-2 375612fb schottky rectifer selection the power schottky diode conducts current during the interval when the switch is turned off. select a diode rated for the maximum sw voltage. if using the pwm feature for dimming, it is important to consider diode leakage, which increases with the temperature, from the output during the pwm low interval. therefore, choose the schottky diode with suffciently low leakage current. table 4 has some recommended component vendors. table 4. schottky rectifer manufacturers vendor web on semiconductor www.onsemi.com diodes, inc. www.diodes.com central semiconductor www.centralsemi.com sense resistor selection the resistor, r sense , between the source of the exter- nal nmos fet and gnd should be selected to provide adequate switch current to drive the application without exceeding the 108mv (typical) current limit threshold on the sense pin of lt3756. for buck mode applications, select a resistor that gives a switch current at least 30% greater than the required led current. for buck mode, select a resistor according to: r sense,buck 0.07v i led for buck-boost, select a resistor according to: r sense,buck-boost v in ? 0.07v v in + v led ( ) i led for boost, select a resistor according to: r sense,boost v in ? 0.07v v led ? i led the placement of r sense should be close to the source of the nmos fet and gnd of the lt3756. the sense input to lt3756 should be a kelvin connection to the positive terminal of r sense . these equations provide an estimate of the sense resistor value based on reasonable assumptions about induc- tor current ripple during steady state switching. lower values of sense resistor may be required in applications where inductor ripple current is higher. examples include applications with current limited operation at high duty cycle, and those with discontinuous conduction mode (dcm) switching. it is always prudent to verify the peak inductor current in the application to ensure the sense resistor selection provides margin to the sense current limit threshold. inductor selection the inductor used with the lt3756 should have a saturation current rating appropriate to the maximum switch current selected with the r sense resistor. choose an inductor value based on operating frequency, input and output voltage to provide a current mode ramp on sense during the switch on-time of approximately 20mv magnitude. the following equations are useful to estimate the inductor value for continuous conduction mode operation: l buck = r sense ? v led v in ? v led ( ) v in ? 0.02v ? f osc l buck-boost = r sense ? v led ? v in v led + v in ( ) ? 0.02v ? f osc l boost = r sense ? v in v led ? v in ( ) v led ? 0.02v ? f osc table 5 provides some recommended inductor vendors. table 5. inductor manufacturers vendor web sumida www.sumida.com wrth elektronik www.we-online.com coiltronics www.cooperet.com vishay www.vishay.com coilcraft www.coilcraft.com a pplica t ions i n f or m a t ion
lt3756/lt3756-1/lt3756-2 375612fb a pplica t ions i n f or m a t ion loop compensation the lt3756 uses an internal transconductance error ampli- fer whose vc output compensates the control loop. the external inductor, output capacitor and the compensation resistor and capacitor determine the loop stability. the inductor and output capacitor are chosen based on performance, size and cost. the compensation resistor and capacitor at vc are selected to optimize control loop response and stability. for typical led applications, a 2.2nf compensation capacitor at vc is adequate, and a series resistor should always be used to increase the slew rate on the vc pin to maintain tighter regulation of led current during fast transients on the input supply to the converter. board layout the high speed operation of the lt3756 demands careful attention to board layout and component placement. the exposed pad of the package is the only gnd terminal of the ic and is also important for thermal management of the ic. it is crucial to achieve a good electrical and thermal contact between the exposed pad and the ground plane of the board. to reduce electromagnetic interference (emi), it is important to minimize the area of the high dv/dt switching node between the inductor, switch drain and anode of the schottky rectifer. use a ground plane under the switching node to eliminate interplane coupling to sensitive signals. the lengths of the high di/dt traces: 1) from the switch node through the switch and sense resistor to gnd, and 2) from the switch node through the schottky rectifer and flter capacitor to gnd should be minimized. the ground points of these two switching current traces should come to a common point then connect to the ground plane under the lt3756. likewise, the ground terminal of the bypass capacitor for the intv cc regulator should be placed near the gnd of the switching path. typically, this requirement will result in the external switch being closest to the ic, along with the intv cc bypass capacitor. the ground for the compensation network and other dc control signals should be star connected to the underside of the ic. do not extensively route high impedance signals such as fb and vc, as they may pick up switching noise. in particular, avoid routing fb and pwmout in parallel for more than a few millimeters on the board. likewise, minimize resistance in series with the sense input to avoid changes (most likely reduction) to the switch current limit threshold.
lt3756/lt3756-1/lt3756-2 375612fb a pplica t ions i n f or m a t ion 4 c ss 3 2 1 9 m1 gnd v in c in l1 10 11 12 13 14 15 16 8 7 6 5 4 3 3 2 1 5 6 1 2 r sense 7 8 c c pwm v ref ctrl r c v out via vias to ground plane openled x x r t r2 r1 r3 r4 r led 375612 f05 led + led ? m2 c out c out d1 component designations refer to ?30w white led headlamp driver with thermal derating? schematic cv cc figure 5. boost converter suggested layout
lt3756/lt3756-1/lt3756-2 375612fb typical a pplica t ions 30w white led headlamp driver with thermal derating v (isp C isn) threshold vs temperature for ntc resistor divider v in lt3756-2 l1, 22h d1 gnd v c intv cc shdn /uvlo fb v ref isp 16.9k 100k intv cc r1 1m c in 4.7f c c 0.001f c ss 0.01f v in 8v to 60v (100v transient) r2 185k r c 10k r t 28.7k 375khz m1: vishay siliconix si7454dp d1: diodes inc pds5100 l1: coiltronics dr127-220 rt1: murata ncp18wm104j m2: vishay siliconix si2328ds c vcc 4.7f see suggested layout, figure 5 100k ntc rt1 ctrl r sense 0.018 r led 0.27 r3 1m m1 m2 r4 14k 370ma c out 4.7f 30w led string 375612 ta02a openled pwm ss rt isn gate sense pwmout temperature (c) 25 0 v (isp ? isn) threshold (mv) 40 80 45 65 105 85 120 20 60 100 125 375512 ta02b
lt3756/lt3756-1/lt3756-2 0 375612fb typical a pplica t ions buck-boost mode led driver v in lt3756-2 l1 68h gndv c intv cc shdn /uvlo fb v ref isp 1m 0.1f v in 9v to 65v v in v in v out l1: coilcraft mss1038-683 d1: on semiconductor mbrs3100t3 m1: vishay siliconix si2328ds m2: zetex zxm6ip03f q1: zetex fmmt493 185k 35.7k 300khz 39k 4700pf c2 2.2f 10v ctrl 1.5k 1k 1m q1 m2 13k 1 m1 0.068 d1 c3 4.7f 375612 ta03a openled pwm ss rt isn gate sense pwmout c1 4.7f 1f 100v 24v to 32v led string 100ma 100k intv cc effciency vs v in 90% effcient, 20w sepic led driver effciency vs v in v in lt3756-2 l1a 33h 1:1 gnd v c intv cc shdn /uvlo fb v ref isp 100k intv cc 1m c1 4.7f 100v 0.001f 0.01f l1: coilcraft msd1278t-333 m1: vishay siliconix si7430dp d1: on semiconductor mbrs3200t m2: zetex zxm61n03f v in 8v to 80v 185k 25k l1b 30k 28.7k 400khz c2 4.7f 10v ctrl 0.033 0.1 511k m2 m1 1a d1 c4 1f c3 10f s2 35v 20w led string 375612 ta04a openled pwm ss rt isn gate sense pwmout v in (v) 0 50 efficiency (%) 60 70 80 90 100 20 40 60 375612 ta03b 80 v in (v) 0 80 efficiency (%) 84 88 92 96 100 20 40 60 375612 ta04b 80
lt3756/lt3756-1/lt3756-2 375612fb mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev a) p ackage descrip t ion msop (mse16) 0608 rev a 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 1 2 3 4 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0o ? 6o typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.305 p 0.038 (.0120 p .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 p 0.102 (.112 p .004) 2.845 p 0.102 (.112 p .004) 4.039 p 0.102 (.159 p .004) (note 3) 1.651 p 0.102 (.065 p .004) 1.651 p 0.102 (.065 p .004) 0.1016 p 0.0508 (.004 p .002) 3.00 p 0.102 (.118 p .004) (note 4) 0.280 p 0.076 (.011 p .003) ref 4.90 p 0.152 (.193 p .006) mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev a) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref
lt3756/lt3756-1/lt3756-2 375612fb p ackage descrip t ion ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691) 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions 1.45 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 bottom view?exposed pad 1.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 0.05 3.50 0.05 0.70 0.05 0.00 ? 0.05 (ud16) qfn 0904 0.25 0.05 0.50 bsc package outline
lt3756/lt3756-1/lt3756-2 375612fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number b 03/10 revised entire data sheet to include h-grade 1-24 (revision history begins at rev b)
lt3756/lt3756-1/lt3756-2 375612fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0310 rev b ? printed in usa r ela t e d p ar t s typical a pplica t ion buck mode 1a led driver with high dimming ratio and open led reporting effciency vs v in part number description comments lt3474 36v, 1a (i led ), 2mhz, step-down led driver v in : 4v to 36v, v out(max) = 13.5v, true color pwm dimming = 400:1, i sd < 1a, tssop16e package lt3475 dual 1.5a (i led ), 36v, 2mhz step-down led driver v in : 4v to 36v, v out(max) = 13.5v, true color pwm dimming = 3000:1, i sd < 1a, tssop20e package lt3476 quad output 1.5a, 36v, 2mhz high current led driver with 1000:1 dimming v in : 2.8v to 16v, v out(max) = 36v, true color pwm dimming = 1000:1, i sd < 10a, 5mm 7mm qfn package lt3477 3a, 42v, 3mhz boost, buck-boost, buck led driver v in : 2.5v to 25v, v out(max) = 40v, dimming = analog/pwm, i sd < 1a, qfn and tssop20e packages lt3478/lt3478-1 4.5a, 42v, 2.5mhz high current led driver with 3000:1 dimming v in : 2.8v to 36v, v out(max) = 42v, true color pwm dimming = 3000:1, i sd < 3a, tssop16e package lt3486 dual 1.3a, 2mhz high current led driver v in : 2.5v to 24v, v out(max) = 36v, true color pwm dimming = 1000:1, i sd < 1a, 5mm 3mm dfn and tssop16e packages lt3496 triple 0.75a, 2.1mhz, 45v led driver v in : 3v to 30v, v out(max) = 45v, dimming = 3000:1, i sd < 1a, 4mm 5mm qfn and tssop16e packages lt3517 1.5a, 2.5mhz, 45v led driver v in : 3v to 30v, v out(max) = 45v, dimming = 3000:1, i sd < 1a, 4mm 4mm qfn and tssop16e packages lt3518 2.3a, 2.5mhz, 45v led driver v in : 3v to 30v, v out(max) = 45v, dimming = 3000:1, i sd < 1a, 4mm 4mm qfn and tssop16e packages lt3755/lt3755-1/ lt3755-2 40v in , 75v out , full featured led controller v in : 4.5v to 40v, v out(max) = 75v, true color pwm dimming = 3000:1, i sd < 1a, 3mm 3mm qfn-16 and ms16e packages ltc ? 3783 high current led controller v in : 3v to 36v, v out(max) = ext fet, true color pwm dimming = 3000:1, i sd < 20a, 5mm 4mm qfn10 and tssop16e packages v in lt3756-2 gnd vc intv cc shdn/uvlo fb v ref v in intv cc isp 0.001f 0.1f v in 24v to 80v 28.7k 375khz 47k 100k c2 4.7f ctrl 0.033 0.1 m1 c3 4.7f s5 25v c4 4.7f l1 33h d1 1a 375612 ta05a openled pwm ss rt isn gate pwmout sense 1m 61.9k m1: vishay siliconix si3430dv d1: diodes inc b1100/b l1: wrth 74456133 m2: vishay siliconix si5435bdc q1: zetex fmmt493 q2: zetex fmmt593 c1 1f s2 200k 20k 5 white leds 20w 200k 200k 1k 1.5k q1 q2 m2 v in (v) 20 80 efficiency (%) 84 88 92 96 100 40 60 375612 ta05b 80 30 50 70 pwm dimming waveforms 10s/div 0a i led 1a v sw 50v/div v pwm 375612 ta05c

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